Low leakage mim capacitor

ABSTRACT

Capacitor structures for use in integrated circuits and methods of their manufacture. The capacitor structures include a bottom electrode, a top electrode and a dielectric layer interposed between the bottom electrode and the top electrode. The capacitor structures further include a metal oxide buffer layer interposed between the dielectric layer and at least one of the bottom and top electrodes. Each metal oxide buffer layer acts to improve capacitance and reduce capacitor leakage. The capacitors are suited for use as memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

This application is a Continuation of U.S. application Ser. No.11/932,512, filed Oct. 31, 2007, which is a Divisional of U.S.application Ser. No. 10/215,462 filed Aug. 9, 2002, issued as U.S. Pat.No. 7,368,343, which is a Divisional of U.S. application Ser. No.09/745,114, filed Dec. 20, 2000, issued as U.S. Pat. No. 7,378,719, allof which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present invention relates generally to metal-insulator-metalsemiconductor capacitors, and in particular to development ofsemiconductor capacitor structures having a buffer layer, and apparatusincluding such capacitor structures.

BACKGROUND

Many electronic systems include a memory device, such as a DynamicRandom Access Memory (DRAM), to store data. A typical DRAM includes anarray of memory cells. Each memory cell includes a capacitor that storesthe data in the cell and a transistor that controls access to the data.The capacitor typically includes two conductive electrodes separated bya dielectric layer. The charge stored across the capacitor isrepresentative of a data bit and can be either a high voltage or a lowvoltage. Data is stored in the memory cells during a write mode andretrieved from the memory cells during a read mode. The data istransmitted on signal lines, sometimes referred to as digit lines, whichare coupled to input/output (I/O) lines through transistors used asswitching devices. Typically, for each bit of data stored, its truelogic state is available on an I/O line and its complementary logicstate is available on an I/O complement line. However, each such memorycell is coupled to, or associated with, only one digit line of a digitline pair through an access transistor.

Typically, the memory cells are arranged in an array and each cell hasan address identifying its location in the array. The array includes aconfiguration of intersecting conductive lines, and memory cells areassociated with the intersections of the lines. In order to read from orwrite to a cell, the particular cell in question must be selected, oraddressed. The address for the selected cell is represented by inputsignals to a word line or row decoder and to a digit line or columndecoder. The row decoder activates a word line in response to the wordline address. The selected word line activates the access transistorsfor each of the memory cells in communication with the selected wordline. The column decoder selects a digit line pair in response to thedigit line address. For a read operation, the selected word lineactivates the access transistors for a given word line address, thecharge of the selected memory cells, i.e the charge stored in theassociated capacitor, are shared with their associated digit lines, anddata is sensed and latched to the digit line pairs.

As DRAMs increase in memory cell density by decreasing memory cell area,there is an ongoing challenge to maintain sufficiently high storagecapacitance despite decreasing memory cell area and its accompanyingcapacitor area, since capacitance is generally a function of electrodearea. Additionally, there is a continuing goal to further decreasememory cell area.

A principal method of increasing cell capacitance is through cellstructure techniques. Such techniques include three-dimensional cellcapacitors, such as trenched or stacked capacitors. One common form ofstacked capacitor structure is a cylindrical container stackedcapacitor, with a container structure forming the bottom electrode ofthe capacitor. Such container structures may have shapes differing froma substantially cylindrical form, such as an oval or otherthree-dimensional container. The container structures may furtherincorporate fins.

Another method of increasing cell capacitance is through the use of highdielectric constant material in the dielectric layer of the capacitor.In order to achieve the charge storage efficiency generally needed in256 megabit (Mb) memories and above, materials having a high dielectricconstant, and typically dielectric constants greater than 20, can beused in the dielectric layer between the bottom electrode and the topelectrode of the capacitor. The dielectric constant is a characteristicvalue of a material and is generally defined as the ratio of the amountof charge that can be stored in the material when it is interposedbetween two electrodes relative to the charge that can be stored whenthe two electrodes are separated by a vacuum.

Unfortunately, high dielectric constant materials are often incompatiblewith existing processes. One cause of such incompatibility can beadverse chemical reactions or oxygen diffusion between the material ofthe dielectric layer and the material of an adjoining electrode due todirect contact.

For the reasons stated above, and for other reasons which will becomeapparent to those skilled in the art upon reading and understanding thepresent specification, there is a need in the art for alternativecapacitor structures and methods for producing same.

SUMMARY

The above mentioned problems with capacitors and associated memorydevices, and other problems are addressed by the present invention andwill be understood by reading and studying the following specification.

Embodiments of the invention include capacitors having a metal oxidebuffer layer interposed between an electrode and a dielectric layer, andmethods of their formation. The metal oxide buffer layer acts to reduceundesirable charge leakage from the capacitor.

For one embodiment, the invention includes a capacitor. The capacitorincludes two electrodes and a dielectric layer interposed therebetween.The capacitor further includes a metal oxide buffer layer interposedbetween the dielectric layer and one of the electrodes.

For one embodiment, the bottom electrode, the top electrode or bothelectrodes contain metal nitride. For another embodiment, the dielectriclayer contains at least one metal oxide dielectric material. For yetanother embodiment, the metal oxide buffer layer contains a metal oxidehaving a composition of the form MO_(x). The metal component M may be arefractory metal. In one embodiment of the invention, the refractorymetal is tungsten (W). In one embodiment, the electrode adjacent thebuffer layer also includes tungsten. In another embodiment of theinvention, the dielectric layer is a metal oxide.

For another embodiment, the invention includes a method of forming acapacitor. The method includes forming a metal oxide buffer layeradjacent of the electrode layers. In one embodiment, the method includesforming a first electrode layer, forming the metal oxide buffer layeradjacent on the first electrode layer, forming a dielectric layer on themetal oxide buffer layer, and forming a second electrode layer on thedielectric layer. In one embodiment of the invention, the methodincludes oxidizing the first electrode to form a thin metal oxide bufferlayer. In another embodiment of the invention, the thin buffer layer isannealed to further reduce capacitor leakage. In another embodiment ofthe invention, the anneal temperature of the buffer layer is about 700degrees. In another embodiment, the buffer layer is annealed for aboutone minute.

Further embodiments of the invention include semiconductor structuresand methods of varying scope, as well as apparatus, devices, modules andsystems making use of such semiconductor structures and methods.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an elevation view of a layout of a portion of a memory arrayof a memory device according to the teachings of the present invention.

FIGS. 2A-2I are cross-sectional views of a portion of the memory deviceof FIG. 1 at various processing stages according to the teachings of thepresent invention.

FIG. 3 is a block diagram of an integrated circuit memory device.

FIG. 4 is an elevation view of a wafer containing semiconductor dies.

FIG. 5 is a block diagram of a circuit module.

FIG. 6 is a block diagram of a memory module.

FIG. 7 is a block diagram of a electronic system.

FIG. 8 is a block diagram of a memory system.

FIG. 9 is a block diagram of a computer system.

FIG. 10 is a graph of capacitor leakage versus capacitance for threedifferent annealing temperatures.

FIG. 11 is an X-ray diffraction spectra of O₃ annealed WN_(x) atdifferent temperatures.

FIG. 12 is a graph of the impact of backend annealing in H₂ onperformance of a capacitor according to the present invention.

DESCRIPTION OF THE EMBODIMENTS

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings which form a part hereof,and in which is shown by way of illustration specific embodiments inwhich the inventions may be practiced. These embodiments are describedin sufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may beutilized and that process, electrical or mechanical changes may be madewithout departing from the scope of the present invention. The termswafer and substrate used in the following description include any basesemiconductor structure. Both wafer and substrate are to be understoodas including silicon-on-sapphire (SOS) technology, silicon-on-insulator(SOI) technology, thin film transistor (TFT) technology, doped andundoped semiconductors, epitaxial layers of a silicon supported by abase semiconductor structure, as well as other semiconductor structuresknown to one skilled in the art. Furthermore, when reference is made toa wafer or substrate in the following description, previous processsteps may have been utilized to form regions/junctions on the basesemiconductor structure, and terms wafer or substrate include theunderlying layers containing such regions/junctions. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

The following description will be illustrated in the context ofsemiconductor container capacitors, and in particular, containercapacitor memory cells for dynamic memory devices. It will be apparentto those skilled in the art that other capacitor structures, e.g.,trench capacitors and parallel plate capacitors, are suitable for usewith the various embodiments of the invention. It will further beapparent to those skilled in the art that the capacitor structuresdescribed herein and their methods of fabrication can be adapted to avariety of integrated circuit devices and applications, some of whichmay be apart from memory devices. Accordingly, the structures of thepresent invention described herein are not limited to the exampleembodiments.

FIG. 1 depicts the general layout of a portion of a memory array of amemory device in accordance with one embodiment of the invention. Thememory array includes container capacitor memory cells 200 formedoverlying active areas 208. Active areas 208 are separated by fieldisolation regions 210. Active areas 208 and field isolation regions 210are formed overlying a semiconductor substrate.

The memory cells 200 are arrayed substantially in rows and columns.Shown in FIG. 1 are portions of three rows 201A, 201B and 201C,collectively 201. Separate digit lines (not shown) would be formedoverlying each row 201 and coupled to active areas 208 through digitline contacts 206. Word lines 202 and 204 are further coupled to activeareas 208, with word lines 202 coupled to active areas 208 in row 201Band word lines 204 coupled to active areas 208 in rows 201A and 201C.The word lines 202 and 204, coupled to memory cells in this alternatingfashion, generally define the columns of the memory array. This foldedbit-line architecture is known to one of ordinary skill for permittinghigher densities of memory cells 200 on a substrate.

FIGS. 2A-2I depict one embodiment of a portion of the processing tofabricate the memory device of FIG. 1. FIGS. 2A-2I are cross-sectionalviews taken along line A-A′ of FIG. 1 during various processing stages.

In FIG. 2A, field isolation regions 210 are formed on a substrate 205.Substrate 205 may be a silicon substrate, such as a P-type siliconsubstrate. Field isolation regions 210 are generally formed of aninsulator material, such as silicon oxides, silicon nitrides or siliconoxynitrides. For this embodiment, field isolation regions 210 are formedof silicon dioxide such as by conventional local oxidation of silicon(LOCOS) which creates substantially planar regions of oxide on thesubstrate surface. Active areas 208 are those areas not covered by thefield isolation regions 210 on substrate 205. The creation of the fieldisolation regions 210 is preceded or followed by the formation of a gatedielectric layer 212. For this embodiment, gate dielectric layer 212 isa thermally grown silicon dioxide, but may be other insulator materialsdescribed herein or known in the art.

Following the creation of the field isolation regions 210 and gatedielectric layer 212, a first conductively doped gate polysilicon layer216, a gate barrier layer 218, a gate conductor layer 220, a gate caplayer 222 and gate spacers 214 are formed by methods known in the art.Gate barrier layer 218 may be a metal nitride, such as titanium nitrideor tungsten nitride. Gate conductor layer 220 may be any conductivematerial, for example a metal. Gate cap layer 222 is often siliconnitride while gate spacers 214 are generally of an insulator materialsuch as silicon oxide, silicon nitride and silicon oxynitride. Theforegoing layers are patterned to form word lines 202 and 204 as gatesfor field effect transistors (FET), which FET's are one type of accessdevices to a data storage unit (capacitor) in a memory cell. Theconstruction of the word lines 202 and 204 are illustrative only. As afurther example, the construction of the word lines 202 and 204 mayinclude a refractory metal silicide layer overlying a polysilicon layer.The metals of chromium (Cr), cobalt (Co), hafnium (Hf), molybdenum (Mo),niobium (Nb), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V)and zirconium (Zr) are generally recognized as refractory metals. Otherconstructions for word lines 202 and 204 are known to those skilled inthe art.

Source/drain regions 228 are formed in the substrate 205 such as byconductive doping of the substrate. Source/drain regions have aconductivity opposite the substrate 205. For a P-type substrate,source/drain regions 228 would have an N-type conductivity. Suchconductive doping may be accomplished through ion implantation ofphosphorus or arsenic for this embodiment. As is often the case,source/drain regions 228 include lightly-doped regions 230 created bydifferential levels of ion concentration or even differing dopant ions.Word lines 202 and 204 are adapted to be coupled to periphery contacts(not shown). The periphery contacts are located at the end of the memoryarray and are adapted for electrical communication with externalcircuitry.

The formation of the word lines 202 and 204 as described are an exampleof one application to be used in conjunction with various embodiments ofthe invention. Other methods of fabrication and other applications arealso feasible and perhaps equally viable. For clarity and to focus onthe formation of the capacitor structures, many of the reference numbersare eliminated from subsequent drawings, e.g., those pertaining to thestructure of the word lines and the source/drain regions.

In FIG. 2B, a thick insulating layer 235 is deposited overlyingsubstrate 205, as well as word lines 202 and 204, field isolationregions 210 and active areas 208. Insulating layer 235 is an insulatormaterial such as silicon oxide, silicon nitride and silicon oxynitridematerials. For one embodiment, insulating layer 235 is a doped insulatormaterial such as borophosphosilicate glass (BPSG), a boron andphosphorous-doped silicon oxide. It is understood that other insulatingmaterials known to those of skill in the art may be used. The insulatinglayer 235 is planarized, such as by chemical-mechanical planarization(CMP), in order to provide a uniform height. A mask 237 is formedoverlying insulating layer 235 and patterned to define future locationsof capacitors.

In FIG. 2C, portions of insulating layer 235 exposed by patterned mask237 are removed and mask 237 is subsequently removed. The portions ofinsulating layer 235 may be removed by etching or other suitable removaltechnique known to those skilled in the art. Removal techniques aregenerally dependent upon the material of construction of the layer to beremoved as well as the surrounding layers to be retained. Patterning ofinsulating layer 235 creates openings having bottom portions 236Aoverlying exposed portions of the substrate 205 and sidewalls 236Bdefined by the insulating layer 235.

In FIG. 2D, a layer of doped polysilicon is formed overlying exposedportions of active area 208 and top portions of insulating layer 235 toform contact layer 240. Contact layer 240 may be formed by controlleddeposition of polysilicon as shown in FIG. 2D. Alternatively, contactlayer 240 may be blanket deposited polysilicon followed by an etch-backto leave a layer of polysilicon overlying exposed portions of activearea 208 between word lines 202 and 204. For still further embodiments,contact layer 240 is formed from tungsten, titanium nitride, tungstennitrides, tantalum nitride, aluminum or other conductive materials,metals or alloys.

In FIG. 2E, the portions of contact layer 240 overlying insulating layer235 are removed leaving contacts 240 between the word lines 202 and 204.A bottom electrode 245 is formed overlying the contacts 240 andinsulating layer 235. Bottom electrode 245 is any conductive material.For one embodiment, bottom electrode 245 contains a metal nitride. Foranother embodiment, the metal component of the bottom electrode 245 is arefractory metal, resulting in a refractory metal nitride. For yetanother embodiment, bottom electrode 245 contains tungsten nitride(WN_(n); 0<n<=6).

Bottom electrode 245 may be formed by any method, such as collimatedsputtering, chemical vapor deposition (CVD) or other depositiontechniques. In the case of a metal nitride material, bottom electrode245 may be deposited as a metal layer followed by nitridation.

Bottom electrode 245 forms the bottom conductive layer or electrode ofthe capacitor. For one embodiment, the bottom conductive layer has aclosed bottom and sidewalls extending up from the closed bottom as shownin FIG. 2E. For another embodiment, the bottom conductive layer has asubstantially planar surface as in a parallel plate capacitor. Bottomelectrode 245 may contain more than one conductive layer, e.g., a metalnitride layer overlying a metal silicide layer. Subsequent annealing ofthe memory device may produce a reaction between bottom electrode 245and contact 240 such that an interface layer is formed. As an example,where bottom electrode 245 contains a refractory metal or refractorymetal nitride, and contact 240 contains polysilicon, subsequentannealing can produce a refractory metal silicide interface betweenbottom electrode 245 and contact 240. Such metal silicide interfacelayers are often advantageous in reducing electrical resistance tocontact 240.

In FIG. 2F, a buffer layer 250 is formed overlying bottom electrode 245.The buffer layer 250 is shown to be directly adjoining bottom electrode245. But buffer layer 250 is not shown to scale relative to bottomelectrode 245 for convenience and clarity of illustration. Buffer layer250 is a metal oxide material having a composition of the form MO_(x).In one embodiment, the metal component M is a refractory metal. Therefractory metals of chromium (Cr), cobalt (Co), hafnium (Hf),molybdenum (Mo), niobium (Nb), tantalum (Ta), titanium (Ti), tungsten(W), vanadium (V) and zirconium (Zr) are included in this definition.For one embodiment, buffer layer 250 contains a tungsten oxide material(WO_(x)). Metal oxide buffer layers can act to reduce capacitor leakage.

Benefits may be derived by matching the metal oxide buffer layer to theadjacent metal nitride electrode. For example, the WO_(x) buffer layer250 can be grown by oxidizing the WN_(x) bottom electrode layer 245.Accordingly, the metal component of the metal oxide buffer layer 250 andthe metal component of the metal nitride of bottom electrode 245 areboth tungsten. Such matching of the buffer layer to the electrode can beutilized to reduce stress between the two layers, thus improving devicereliability. Furthermore, such matching allows formation of bottomelectrode 245 and buffer layer 250 using a single deposition processalong with an oxidation process.

For one embodiment, buffer layer 250 is formed from the bottom electrode245 containing metal nitride. For this embodiment, the metal nitride ofthe bottom electrode 245 is oxidized to form the metal oxide. Suchoxidation may use a variety of techniques including oxidation in anambient containing O₂ or ozone (O₃), with or without the help of plasma,or UV light or remote plasma. Controlled oxidation of the metal nitridecan be used to form the metal oxide buffer layer 250, at the upper,exposed surface of bottom electrode 245. For a further embodiment,buffer layer 250 is grown by oxidizing a WN_(x) bottom electrode 245 inan oxygen-containing ambient thereby using tungsten at the surface ofthe bottom electrode to grow a WO₃ buffer layer. In one embodiment, thebuffer layer 250 is grown in an O₂ or O₃ ambient at a temperature in therange of 300 to 550 degrees Celsius. The buffer layer 250 may be grownwith or without a plasma in the environment. The bottom electrode 245now includes W₂N film adjacent the WO₃ buffer layer 250 due to theoxidation process.

In one embodiment, buffer layer 250, bottom electrode 245 and substrateare annealed at a temperature of at least 700 degrees Celsius in aninert gas ambient. The inert gases include, but are not limited to, N₂,Ar, or He. The buffer layer is believed to have an orthorhomiccrystalline structure due to the high temperature anneal.

In FIG. 2G, a dielectric layer 255 is formed overlying buffer layer 250.The dielectric layer 255 is shown to be adjoining buffer layer 250, butthere is no prohibition to forming additional layers interposed betweendielectric layer 255 and buffer layer 250 as same may be suitable insome applications of the present invention. Note, however, that thenature of any additional layer may adversely affect performance of theresulting capacitor such as creating an undesirable series capacitance.

Dielectric layer 255 contains a dielectric material. For one embodiment,dielectric layer 255 contains at least one metal oxide dielectricmaterial. For another embodiment, dielectric layer 255 contains aTantalum Oxide, such as Ta₂O₅. Dielectric layer 255 may be deposited byany deposition technique, e.g., RF-magnetron sputtering, chemical vapordeposition (CVD). As one example, a metal oxide, e.g., tantalum oxide,may be formed by depositing a layer of the metal component, e.g.,tantalum, followed by annealing in an oxygen-containing ambient. Asanother example, the metal oxide may be deposited by metal organicchemical vapor deposition (MOCVD). Subsequent to formation, dielectriclayer 255 may be annealed in an oxygen-containing ambient, such as anambient containing O₂ or ozone, at a temperature within the range ofapproximately 200 to 800° C. The actual oxygen-containing ambient,concentration of oxygen species and annealing temperature may vary forthe specific dielectric deposited. These variations are known to thoseskilled in the art.

Bottom electrode 245 is generally not oxidized, or is only marginallyoxidized, during formation or subsequent processing of dielectric layer255 due to the protection from the oxygen-containing ambient anddiffusion of oxygen as provided by buffer layer 250. However, insulatorsgenerally create a series capacitance of the buffer layer and thedielectric layer. Such series capacitance can detrimentally impact theoverall capacitance of the capacitor structure when the insulativebuffer layer has a dielectric constant less than that of the dielectriclayer. Accordingly, the buffer layer has a dielectric constant greaterthan the dielectric constant of the dielectric layer. For example, theWO₃ buffer layer has a dielectric constant of about 300 and a Ta₂O₅dielectric layer has a dielectric constant of about 20-25. Accordingly,the dielectric layer determines the capacitance with little detrimentaleffect, e.g. series capacitance, by the buffer layer.

In FIG. 2H, a top electrode 265 is deposited to form the top conductivelayer or electrode of the capacitor. The top electrode 265 is shown tobe directly adjoining dielectric layer 255, but there is no prohibitionto forming additional conductive layers interposed between the topelectrode 265 and dielectric layer 255. Top electrode 265 may be of anyconductive material and generally follows the same guidelines as bottomelectrode 245. For one embodiment, top electrode 265 contains Pt—Rhdeposited by CVD. Layers 245 through 270 are then patterned bytechniques known in the art to define capacitors of memory cells 200 inFIG. 2I.

In addition, the figures were used to aid the understanding of theaccompanying text. However, the figures are not drawn to scale andrelative sizing of individual features and layers are not necessarilyindicative of the relative dimensions of such individual features orlayers in application. As an example, while bottom electrode 245 isdrawn to have an illustrated thickness of approximately the same asdielectric layer 255, for purposes of clarity and convenience, bottomelectrode 245 may have a physical thickness of five times that ofdielectric layer 255 in some applications. In one embodiment, bottomelectrode 245 has a thickness of about 200-400 A. In one embodiment, thebuffer layer has a thickness of about 50-150 A. In one embodiment, thedielectric layer 255 has a thickness of about 60-100 A. In oneembodiment, the top electrode 265 has a thickness of about 200-800 A.One of ordinary skill in the art will understand upon reading thedisclosure the suitable thicknesses of such layers for carrying out thepresent invention. Accordingly, the drawings are not to be used fordimensional characterization.

While the foregoing embodiments of capacitor structures may be used in avariety of integrated circuit devices, they are particularly suited foruse as storage capacitors of memory cells found in dynamic memorydevices.

Memory Devices

FIG. 3 is a simplified block diagram of a memory device according to oneembodiment of the invention. The memory device 300 includes an array ofmemory cells 302, address decoder 304, row access circuitry 306, columnaccess circuitry 308, control circuitry 310, and Input/Output circuit312. The memory can be coupled to an external microprocessor 314, ormemory controller for memory accessing. The memory receives controlsignals from the processor 314, such as WE*, RAS* and CAS* signals. Thememory is used to store data which is accessed via I/O lines. It will beappreciated by those skilled in the art that additional circuitry andcontrol signals can be provided, and that the memory device of FIG. 3has been simplified to help focus on the invention. At least one of thememory cells or associated circuitry has a capacitor in accordance withthe present invention.

It will be understood that the above description of a DRAM (DynamicRandom Access Memory) is intended to provide a general understanding ofthe memory and is not a complete description of all the elements andfeatures of a DRAM. Further, the invention is equally applicable to anysize and type of memory circuit and is not intended to be limited to theDRAM described above. Other alternative types of devices include SRAM(Static Random Access Memory) or Flash memories. Additionally, the DRAMcould be a synchronous DRAM commonly referred to as SGRAM (SynchronousGraphics Random Access Memory), SDRAM (Synchronous Dynamic Random AccessMemory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well asSynchlink or Rambus DRAMs and other emerging DRAM technologies.

As recognized by those skilled in the art, memory devices of the typedescribed herein are generally fabricated as an integrated circuitcontaining a variety of semiconductor devices. The integrated circuit issupported by a substrate. Integrated circuits are typically repeatedmultiple times on each substrate. The substrate is further processed toseparate the integrated circuits into dies as is known in the art.

Semiconductor Dies

With reference to FIG. 4, for one embodiment, a semiconductor die 410 isproduced from a wafer 400. A die is an individual pattern, typicallyrectangular, on a substrate that contains circuitry, or integratedcircuit devices, to perform a specific function. A semiconductor waferwill typically contain a repeated pattern of such dies containing thesame functionality. Die 410 may contain circuitry for the inventivememory device, as discussed above. Die 410 may further containadditional circuitry to extend to such complex devices as a monolithicprocessor with multiple functionality. Die 410 is typically packaged ina protective casing (not shown) with leads extending therefrom (notshown) providing access to the circuitry of the die for unilateral orbilateral communication and control. Each die 410 may contain at leastone of the capacitors according to the present invention.

Circuit Modules

As shown in FIG. 5, two or more dies 410 may be combined, with orwithout protective casing, into a circuit module 500 to enhance orextend the functionality of an individual die 410. Circuit module 500may be a combination of dies 410 representing a variety of functions, ora combination of dies 410 containing the same functionality. One or moredies 410 of circuit module 500 contain at least one capacitor inaccordance with the invention.

Some examples of a circuit module include memory modules, devicedrivers, power modules, communication modems, processor modules andapplication-specific modules, and may include multilayer, multichipmodules. Circuit module 500 may be a subcomponent of a variety ofelectronic systems, such as a clock, a television, a cell phone, apersonal computer, an automobile, an industrial control system, anaircraft and others. Circuit module 500 will have a variety of leads 410extending therefrom and coupled to the dies 410 providing unilateral orbilateral communication and control.

FIG. 6 shows one embodiment of a circuit module as memory module 600.Memory module 600 contains multiple memory devices 610 contained onsupport 615, the number generally depending upon the desired bus widthand the desire for parity. Memory module 600 accepts a command signalfrom an external controller (not shown) on a command link 620 andprovides for data input and data output on data links 630. The commandlink 620 and data links 630 are connected to leads 640 extending fromthe support 615. Leads 640 are shown for conceptual purposes and are notlimited to the positions shown in FIG. 6. At least one of the memorydevices 610 contains a capacitor according to the present invention.

Electronic Systems

FIG. 7 shows one embodiment of an electronic system 700 containing oneor more circuit modules 500. Electronic system 700 generally contains auser interface 710. User interface 710 provides a user of the electronicsystem 700 with some form of control or observation of the results ofthe electronic system 700. Some examples of user interface 710 includethe keyboard, pointing device, monitor or printer of a personalcomputer; the tuning dial, display or speakers of a radio; the ignitionswitch, gauges or gas pedal of an automobile; and the card reader,keypad, display or currency dispenser of an automated teller machine.User interface 710 may further describe access ports provided toelectronic system 700. Access ports are used to connect an electronicsystem to the more tangible user interface components previouslyexemplified. One or more of the circuit modules 500 may be a processorproviding some form of manipulation, control or direction of inputs fromor outputs to user interface 710, or of other information eitherpreprogrammed into, or otherwise provided to, electronic system 700. Aswill be apparent from the lists of examples previously given, electronicsystem 700 will often be associated with certain mechanical components(not shown) in addition to circuit modules 500 and user interface 710.It will be appreciated that the one or more circuit modules 500 inelectronic system 700 can be replaced by a single integrated circuit.Furthermore, electronic system 700 may be a subcomponent of a largerelectronic system. It will also be appreciated that at least one of thememory modules 500 contains a capacitor according to the presentinvention.

FIG. 8 shows one embodiment of an electronic system as memory system800. Memory system 800 contains one or more memory modules 600 and amemory controller 810. The memory modules 600 each contain one or morememory devices 610. At least one of memory devices 610 contain acapacitor according to the present invention. Memory controller 810provides and controls a bidirectional interface between memory system800 and an external system bus 820. Memory system 800 accepts a commandsignal from the external bus 820 and relays it to the one or more memorymodules 600 on a command link 830. Memory system 800 provides for datainput and data output between the one or more memory modules 600 andexternal system bus 820 on data links 840. It will also be appreciatedthat at least one of the memory modules 600 contains a capacitoraccording to the present invention.

FIG. 9 shows a further embodiment of an electronic system as a computersystem 900. Computer system 900 contains a processor 910 and a memorysystem 800 housed in a computer unit 905. Computer system 900 is but oneexample of an electronic system containing another electronic system,i.e., memory system 800, as a subcomponent. Computer system 900optionally contains user interface components. Depicted in FIG. 9 are akeyboard 1220, a pointing device 930, a monitor 940, a printer 950 and abulk storage device 960. It will be appreciated that other componentsare often associated with computer system 900 such as modems, devicedriver cards, additional storage devices, etc. It will further beappreciated that the processor 910 and memory system 800 of computersystem 900 can be incorporated on a single integrated circuit. Suchsingle package processing units reduce the communication time betweenthe processor and the memory circuit. It will be appreciated that atleast one of the processor 910 and memory system 800 contain a capacitoraccording to the present invention.

Test Results

FIGS. 10-12 show results from various test wafers. The test wafers allinclude a deep container, high-k MIM capacitor formed of a WN_(x) bottomelectrode deposited by CVD on a substrate, an 80 A Ta₂O₅ dielectriclayer deposited by CVD, and a Pt—Rh alloy top electrode also depositedby CVD. A buffer layer is formed by oxidizing the WN_(x) bottomelectrode prior to depositing the dielectric layer. The test wafers wereoxidized in an O₃ ambient at 475 degrees Celsius for three minutes. Thebuffer layer comprises a WO₃ layer and the bottom electrode includes aW₂N layer adjacent the buffer layer. After creation of the WO₃ bufferlayer and before depositing the dielectric layer, the bufferlayer/bottom electrode stack is annealed in an N₂ ambient for one minuteat various temperatures ranging from 500 to 700 degrees Celsius. Thedielectric layer is deposited at 475 degrees Celsius in an O₂ ambient.The Pt—Rh alloy top electrode is deposited according to techniques knownto those of skill in the art.

FIG. 10 shows capacitance and leakage measurements from three wafershaving a plurality of MIM container capacitors. All capacitors werecreated according to the above method with the WO₃ buffer layers andadjacent electrodes on each wafer being annealed at varioustemperatures. Test capacitors 1 (denoted as _) were created by annealingthe WO₃ buffer layer/electrode stack at a temperature of 500 degreesCelsius. Test capacitors 2 (denoted as □) were created by annealing theWO₃ buffer layer/electrode stack at a temperature of 600 degreesCelsius. Test capacitors 3 (denoted as ♦) were created by annealing theWO₃ buffer layer/electrode stack at a temperature of 700 degreesCelsius. As evident from the plotted data points representing leakageand capacitance, the higher temperature anneal represented by the testcapacitors 3 (denoted as ♦) yields higher capacitance and lower leakagerelative to the lower temperature anneal represented by test capacitors1 and 2 (respectively denoted by _ and □).

FIG. 11 shows an X-ray diffraction spectra of two WO₃ buffer layersamples. The lighter line represents a first sample which was annealedat a temperature of 650 degrees Celsius. The darker data line representsa second sample which was annealed at a temperature of 700 degreesCelsius. Both stacks were annealed in an N₂ ambient for one minute. Thegraph further indicates the peaks of the W₂N layer of the bottom,adjacent electrode. It is noted that the peaks of the W₂N layer samplesdo not shift for the two annealing temperatures. The spectra shows thatthe WO₃ peaks of the 700 degree annealed, second stack shift toward alower 2-theta angle than the WO₃ peaks of the 650 degree annealed, firststack. The shift was about 0.5 to 1 degree. As a result, it isidentified that the 700 degree annealed buffer layer has an orthorhomiccrystal structure, while the 650 degree annealed buffer layer has amonoclinic crystal structure. Orthorhomic structures are more stable athigher temperatures than monoclinic structures.

Shifts in 2-theta angle can at times be attributed to film stress.However, the shift shown in FIG. 11 is believed to not be caused by filmstress as the W₂N peaks did not shift as a function of the differentanneal temperatures.

In one embodiment, the anneal temperature of the buffer layer/electrodestack is about 700 degrees Celsius. As discussed in conjunction with thetest results, a higher anneal temperature of the buffer layer yields acapacitor with higher capacitance and lower leakage. It is believed thatthe high temperature anneal (at about, or greater than, 700 degreesCelsius) changes the phase of the WO₃ lattice structure from amonoclinic crystalline structure to an orthorhomic crystallinestructure, which is more stable than monoclinic lattice structures athigher temperatures.

FIG. 12 graphically shows the effect of backend wafer processing oncapacitor leakage. Integrated circuits that include transistors aresometimes subjected to backend processing which improves the reliabilityof the structures. Backend processing typically includes annealing thewafer in a hydrogen ambient, for example in an ambient of 10% hydrogenand 90% nitrogen. Such backend processing results in a more robustinterface for the transistors. The sets of capacitors denoted by ⋄, +,and ◯ were not subjected to backend processing. The sets of capacitorsdenoted by □, _, and • were respectively fabricated in the same manneras sets of capacitors ⋄, +, and ◯ and then were subject to backendprocessing. All of the capacitors ⋄, +, ◯, □, _, and • have a structureas shown in FIG. 2I. The sets of capacitors denoted by ◯ and • had theirbottom electrodes and buffer layers annealed at 750 degrees Celsius. Thesets of capacitors denoted by + and _ had their bottom electrodes andbuffer layers annealed at 550 degrees Celsius. The sets of capacitorsdenoted by ⋄ and □ did not anneal their bottom electrodes and bufferlayers.

As shown in the graph of FIG. 12, the leakage of the capacitors whichwere not subject to backend processing is less than those capacitorswhich were subject to backend processing. But annealing the bottomelectrode and buffer layer did reduce the leakage compared to notannealing. More specifically, the median leakage of capacitors •, whichwere annealed at 750 degrees Celsius, is about 70 fA. Whereas the medianleakages for capacitors _ and capacitors □, which were respectivelyannealed at 550 degrees Celsius and not annealed, are about 100 fA and200 fA, respectively. Accordingly, the high temperature anneal of thebuffer layer 250 and bottom electrode 245 resulted in capacitors whichhave less leakage than those annealed at lower temperatures or notannealed. It is believed that the capacitors which are subjected to thehigh temperature anneal (greater than 700 degrees Celsius, and in oneembodiment at about 750 degrees Celsius) are more stable and thus lesseffected by the backend hydrogen anneal processing.

The other capacitors (denoted by ⋄, +, and ◯) not subject to backendprocessing have a leakage which is less than the leakage of thecapacitors subjected to backend processing. While not visible on thescale of FIG. 12, these capacitors follow the above findings that thecapacitor with a buffer layer according to the present invention whichis subject to a high temperature anneal has less leakage than thecapacitors which were not subject to a high temperature anneal.

It is foreseen that the present invention can be practiced with orwithout the backend processing. For example, it is possible to createthe transistors on a wafer and then subject same to backend processingprior to creating the capacitors according to the present invention,e.g. capacitor over digit line structures.

While the invention has been described and illustrated with respect toforming container capacitors for a memory cell, it should be apparentthat substantially similar processing techniques can be used to formother container capacitors for other applications as well as othercapacitor structures. As one example, capacitors formed in accordancewith the methods described herein may be used as on-chip capacitorsutilized to reduce lead impedance of a packaged integrated circuit chip.As further example, parallel plate or trench capacitors may be formedwith a metal oxide barrier layer between a dielectric layer and anelectrode.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.For example, other materials and shapes, as well as other deposition andremoval processes, may be utilized in conjunction with the invention.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

CONCLUSION

Capacitor structures and methods of their manufacture have beendescribed for use in integrated circuits. The capacitor structuresinclude two electrodes and a dielectric layer interposed between the twoelectrodes. The capacitor structures further include a metal oxidebuffer layer interposed between the dielectric layer and one of theelectrodes. The metal oxide buffer layer acts to reduce leakage andyield higher capacitance. The capacitors are suited for use in memorycells and apparatus incorporating such memory cells, as well as in otherintegrated circuits.

What is claimed is:
 1. A container capacitor, comprising: a topelectrode; a metal nitride electrode layer as a bottom electrode; adielectric layer interposed between the top electrode and the metalnitride electrode layer; and a metal oxide buffer layer adjacent to themetal nitride electrode layer and interposed between the dielectriclayer and the metal nitride electrode layer, wherein a metal in themetal oxide buffer layer matches the metal in the metal nitrideelectrode layer, and wherein a dielectric constant of the metal oxidebuffer layer is greater than a dielectric constant of the dielectriclayer.
 2. The container capacitor of claim 1, wherein the metalcomponent of the metal oxide buffer layer and the metal nitrideelectrode layer is tungsten (W).
 3. The container capacitor of claim 2,wherein the metal nitride electrode layer includes W₂N and is adjacent atungsten oxide buffer layer that includes WO₃.
 4. The containercapacitor of claim 1, wherein the metal component of the metal oxidebuffer layer and the metal nitride electrode layer is the samerefractory metal.
 5. The container capacitor of claim 1, wherein themetal oxide buffer layer includes an orthorhombic crystalline structure.6. The container capacitor of claim 1, wherein a shape of the containercapacitor is substantially cylindrical.
 7. The container capacitor ofclaim 1, wherein the metal nitride electrode includes a closed bottomand sidewalls extending away from the closed bottom, and wherein across-section of the sidewalls has a substantially oval shape.
 8. Thecontainer capacitor of claim 1, wherein an interface between the metalnitride electrode layer and an electrical contact of the metal nitrideelectrode layer is a refractory metal silicide interface.
 9. Thecontainer capacitor of claim 1, wherein the metal nitride electrodelayer includes a tungsten nitride layer overlying a tungsten silicidelayer.
 10. A memory cell comprising a container capacitor and an accesstransistor, wherein the container capacitor includes: a top electrode; ametal nitride electrode layer as a bottom electrode; a dielectric layerinterposed between the top electrode and the metal nitride electrodelayer; and a metal oxide buffer layer adjacent to the metal nitrideelectrode layer and interposed between the dielectric layer and themetal nitride electrode layer, wherein a metal in the metal oxide bufferlayer matches the metal in the metal nitride electrode layer, andwherein a dielectric constant of the metal oxide buffer layer is greaterthan a dielectric constant of the dielectric layer.
 11. The memory cellof claim 10, wherein the metal in the metal oxide buffer layer and themetal nitride electrode of the container capacitor is tungsten (W). 12.The memory cell of claim 11, wherein the metal nitride electrode layerof the container capacitor includes W₂N and is adjacent a tungsten oxidebuffer layer that includes WO₃.
 13. The memory cell of claim 10, whereinthe metal oxide buffer layer of the container capacitor includes anorthorhombic crystalline structure.
 14. The memory cell of claim 10,wherein an interface between the metal nitride electrode and anelectrical contact of the container capacitor is a refractory metalsilicide interface.
 15. The memory cell of claim 10, wherein the metalnitride electrode of the container capacitor includes a tungsten nitridelayer overlying a tungsten silicide layer.
 16. A memory device,comprising: an array of memory cells, wherein at least a portion of thememory cells includes a data storage capacitor having a containerstructure, wherein the data storage capacitor includes: a top electrode;a metal nitride electrode layer as a bottom electrode; a dielectriclayer interposed between the top electrode and the metal nitrideelectrode layer; and a metal oxide buffer layer adjacent to the metalnitride electrode layer and interposed between the dielectric layer andthe metal nitride electrode layer, wherein a metal in the metal oxidebuffer layer matches the metal in the metal nitride electrode layer, andwherein a dielectric constant of the metal oxide buffer layer is greaterthan a dielectric constant of the dielectric layer.
 17. The memory cellof claim 16, wherein the metal in the metal oxide buffer layer and themetal nitride electrode of the data storage capacitor is tungsten (W).18. The memory cell of claim 17, wherein the metal nitride electrodelayer of the data storage capacitor includes W₂N and is adjacent atungsten oxide buffer layer that includes WO₃.
 19. The memory cell ofclaim 16, wherein an interface between the metal nitride electrode andan electrical contact of the data storage capacitor is a refractorymetal silicide interface.
 20. The memory cell of claim 16, wherein themetal nitride electrode of the data storage capacitor includes atungsten nitride layer overlying a tungsten silicide layer.